1. Field of the Invention
This invention relates generally to an enhancement mode semiconductor device and, more particularly, to an enhancement mode field effect transistor (FET) device that employs a strained N-doped InAlAs charge shield layer and an unintentionally doped InAlAs barrier layer that act to minimize depletion effects on the surface of the device.
2. Discussion of the Related Art
High performance and reliable enhancement mode semiconductor devices, such as enhancement mode field effect transistor (FET) devices, are used for many circuit applications, including analog-to-digital converters, digital FETs, power FETs and cryogenic low noise devices. An enhancement mode FET device is a normally-off device. A normally-off device is a device that does not allow current flow between the source and drain terminals of the FET device when no voltage is applied to the gate terminal. Enhancement mode devices are different in this regard than depletion mode FET devices, which require a potential applied to the gate terminal to allow current flow through the channel between the source terminal and the drain terminal. Enhancement mode FET devices are advantageous in circuit applications because a separate power source for the gate terminal is not required. Depletion mode devices require an additional negative potential applied to the gate terminal for operation. Additionally, enhancement mode FET devices provide higher gain than depletion mode devices.
Conventional methods of fabricating enhancement mode FET devices include etching a relatively deep recess in the device where the gate electrode is deposited and/or diffused into the device. This deep etch positions the gate electrode very close to the FET channel which typically results in electrons tunneling from the gate electrode to the channel. This tunneling reduces control of the device and causes a lower breakdown voltage which results in performance limitations of the enhancement mode FET device. Also, the gate deposition process is inherently uncontrolled because the placement of the gate electrode relative to the channel is dependent upon a wet chemical etchant of varying etching uniformity. Thus, the Schottky barrier height resulting from this process is poor, and the device is subject to deleterious surface depletion effects due to the deep recess.
A new FET device structure needs to be developed to produce a high performance and reliable enhancement mode device that does not suffer from surface depletion effects. It is therefore an object of the present invention to provide such a device structure.
In accordance with the teachings of the present invention, an enhancement mode FET device is disclosed that employs a strained N-doped InAlAs charge shield layer disposed on an intrinsic InAlAs barrier layer. The gate metal electrode of the FET device is controllably diffused through a recess into the shield layer to the barrier layer. The resulting enhancement mode device provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects by charge shielding from the shield layer in the adjacent regions between the recess edge and the gate electrode. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.
Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.